1. Field of the Invention
The present invention relates to microprocessor systems, and more particularly, to a dynamic cache coherency method and apparatus providing enhanced microprocessor system performance.
2. Related Applications
This application is related to copending U.S. patent application Ser. No. 07/977,226, filed Nov. 16, 1992, now abandoned in favor of continuation application Ser. No. 08/400,116, filed Mar. 6, 1995, now U.S. Pat. No. 5,479,636, entitled "Concurrent Cache line Replacement Method and Apparatus In Microprocessor System With Write Back Cache Memory," copending U.S. patent application Ser. No. 07/976,891, filed Nov. 16, 1992, (now abandoned in favor of continuation application Ser. No. 08/508,096 filed Jul. 27, 1995), entitled, "Zero Wait State Cache Using Non-Interleaved Banks Of Asynchronous SRAM, " and copending U.S. patent application Ser. No. 07/977,228, filed Nov. 16, 1992, (now abandoned in favor of continuation application Ser. No. 08/410,010 filed Mar. 23, 1995), entitled, "Pseudo-Concurrent Access to a Shared Resource."
3. Art Background
In order to avoid frequent, cycle consuming accesses of main memory, a microprocessor system frequently utilizes cache memory. A cache memory is typically comprised of a relatively small amount of static random access memory (SRAM) which is both physically faster than main memory and arranged such that it can be addressed more rapidly than main memory. The cache memory is then disposed between the microprocessor and the main memory and used to capture and store instructions and data as they are used by the microprocessor. Once these instructions and data are present in the cache memory, the microprocessor can, thereafter, quickly and advantageously access them in the cache memory rather than in main memory. The intelligent design and management of a cache memory can substantially enhance the performance of the overall microprocessor system.
One of the problems associated with the use of a cache memory in a microprocessor system, however, is the problem of cache coherency. In particular, when a block of data is first placed in the cache memory from main memory the block of data constitutes an exact copy of the block of data as stored in main memory. If the microprocessor, however, later modifies this block of data in cache memory, for example, through a write operation, and fails to similarly modify the corresponding block of data in main memory, the two blocks of data become inconsistent or incoherent. Under such circumstances, the main memory will continue to store what is now a "stale" block of data, while the cache memory stores the proper "updated" block of data. If an input/output (I/O) unit or an additional, associated microprocessor thereafter accesses the block of data in main memory, it improperly accesses a stale block of data. For this reason, as well as others, cache coherency or consistency must be maintained in a microprocessor system.
Two basic solutions to the problem of cache coherency have been devised. The first solution utilizes what is termed "a write through cache." In a write through cache, coherency is maintained by ensuring that whenever a write operation to a block of data in cache memory occurs, a similar write operation is also performed on the corresponding block of data residing in main memory. While this approach effectively guarantees coherency, it also exacts a heavy performance price, as the length of each and every write operation is determined not by the relatively fast time it takes to write to cache memory, but instead, by the relatively slow amount of time it takes to write to main memory.
A second solution which offers higher performance by not exacting as much processor overhead utilizes what is termed "a write back cache." In a write back cache, a write operation to a block of data in cache memory is not immediately accompanied with a similar write operation to the corresponding block of data residing in main memory. Instead, cache coherency is maintained through the use of subsequent and selective write back operations from the cache memory to the main memory. Such write back operations can be made selectively whenever they are required to maintain cache coherency.
One common context in which a write back cache necessarily utilizes a write back occurs in a write back cache when a processor read access results in a cache miss to a modified or "dirty" cache line. In order to avoid an overwriting of the dirty cache line before updating main memory, a write back of the dirty cache line to main memory must occur before the new cache line is placed in the cache. In such a scenario, in prior art systems, two separate operations were performed in serial fashion. First, the older, dirty cache line was written to main memory, then in serial fashion, the new cache line was written from main memory to the former cache line location of the dirty cache line. Such prior art replacement approaches, however, adversely required the processor to wait or stall for the whole duration of the serial replacement operation, resulting in the waste of valuable processor time. A novel method and apparatus which advantageously performs these two operations concurrently is described in U.S. Pat. No. 5,479,636, entitled, "Concurrent Cache Line Replacement Method and Apparatus In Microprocessor System With Write Back Cache Memory." As described in this copending U.S. Patent Application, such a concurrent cache line replacement method and apparatus advantageously reduces processor overhead and thereby enhances the performance of the overall microprocessor system.
As will be described, in accordance with the present invention, processor overhead is also reduced through the use of a dynamic cache coherency method and apparatus. As will be explained, the dynamic cache coherency method and apparatus of the present invention reduces processor overhead by dynamically utilizing a cache memory in a write back mode under certain predefined conditions, and alternatively, utilizing the same cache memory in a write through mode in the event of certain other predefined conditions.